As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin field effect transistor (FinFET). A typical FinFET is fabricated with a thin vertical “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. Having a gate on both sides of the channel allows gate control of the channel from both sides. Further advantages of FinFET comprises reducing the short channel effect and enabling higher current flow.
FIG. 1A shows an isometric view of a conventional FinFET 100, and FIG. 1B illustrates a cross-sectional view of the FinFET 100 taken along the line a-a of FIG. 1A. The fin 104/108 comprises a raised active region 104 above a semiconductor substrate 102. Fin 104/108 is surrounded by a shallow trench isolation (STI) structure 106. A gate structure 110 comprising a gate dielectric 112, a gate electrode 114, and an optional hardmask layer 116 is formed above the fin 104/108. Sidewall spacers 118 are formed on both sides of the gate structure 110. Further, a portion of the fin 104/108 contains strained structures 108 in source and drain (S/D) recess cavities of the FinFET 100. The strained structures 108 are formed after a fin recessing process and an epitaxial growth step. The strained structures 108 utilizing epitaxial silicon germanium (SiGe) may be used to enhance carrier mobility.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, an ordered atomic arrangement does not exist due to lattice mismatch between the portion 104 of the fin 104/108 and strained portions 108. Thus, strain-induced crystal defects 108a may become embedded in the strained structure 108. The crystal defects 108a may provide carrier transportation paths during device operation, thereby increasing the likelihood of device instability and/or device failure.
Accordingly, what is needed is methods for fabricating a reduced-defect strained structure.